PCI-SIG released the final PCI Express 7.0 specification to its members on June 11, 2025, doubling the per-lane transfer rate to 128 gigatransfers per second (GT/s). A 16-lane, or x16, connection supports up to 512 GB/s of combined bidirectional bandwidth before protocol overhead.
PCI-SIG identifies AI and machine learning, hyperscale data centers, high-performance computing, cloud platforms and 800G Ethernet among the standard’s target applications. The specification increases the bandwidth available to connected devices; it does not establish a corresponding increase in application performance.
What the bandwidth figures measure
The 512 GB/s figure combines both directions of an x16 connection: up to 256 GB/s in each direction simultaneously. It describes raw link capacity rather than measured application throughput. Protocol overhead and the capabilities of the connected hardware affect usable throughput.
PCIe 5.0 supports 32 GT/s per lane and approximately 128 GB/s of combined raw bidirectional bandwidth over x16. PCIe 6.0 doubled those figures to 64 GT/s and 256 GB/s. PCIe 7.0 doubles them again.
The specification retains the four-level pulse amplitude modulation, or PAM4, signaling and flit-based encoding introduced with PCIe 6.0. The higher transfer rate comes from increasing the signaling frequency while continuing to use PAM4, rather than introducing a different modulation scheme.
Electrical connections require careful design
PCIe provides connections between processors and devices such as graphics cards, network adapters and storage controllers. In servers, those links form part of the paths used to move data between computing, storage and networking components.
Higher signaling frequencies make maintaining signal integrity over copper connections more demanding. The electrical path must account for signal loss, reflections and crosstalk across board traces, packages, connectors and cables.
Retimers, which receive and retransmit signals to extend a link’s reach, are among the components used to support longer connections. Implementing the standard therefore involves the physical connection and its validation as well as compatible controller silicon.
Gaming results provide a narrower comparison
Existing gaming measurements show why interface bandwidth and frame rates need to be distinguished. In results published in February 2025, the GamersNexus test team compared an Nvidia GeForce RTX 5090 across PCIe 3.0, 4.0 and 5.0 x16 connections using an AMD Ryzen 7 9800X3D system.
The team reported broadly similar performance between PCIe 4.0 and 5.0, with differences of roughly 1% to 4% between PCIe 3.0 and 5.0 across the tested gaming scenarios. Those findings apply to that hardware and test suite. They do not measure PCIe 7.0 or AI performance, or establish results for graphics cards with fewer available lanes.
Specification development also precedes implementation and compliance testing. The release of a standard is a separate milestone from the launch of compatible graphics cards, SSDs or server platforms.
PCI-SIG president Al Yanes described the range of requirements in June 2025: “Not everybody’s going to need PCI-Express 7.0, but we still have PCI-Express at the lower clock rates as well.”
