PCI-SIG has released version 0.5 of the PCI Express 8.0 specification for member review, retaining targets of 256 GT/s per lane and up to 1 TB/s of aggregate bidirectional bandwidth over an x16 connection. Evaluating new connector technology remains among the organization’s development objectives.
PCI-SIG describes version 0.5 as the first official draft, incorporating member feedback following the release of version 0.3 in September 2025. The organization says the completed specification remains on track for release by 2028. The member-review release is an intermediate milestone, rather than a finished standard.
Bandwidth and technical objectives
The proposed 256 GT/s transfer rate is twice the 128 GT/s rate of PCIe 7.0. PCI-SIG’s figure of up to 1 TB/s combines bandwidth in both directions across a full 16-lane connection. It is a specification target, rather than a measured application-performance result.
PCI-SIG’s objectives also include meeting latency, forward error correction and reliability targets, maintaining backward compatibility with earlier PCIe generations, improving bandwidth through protocol enhancements and developing additional techniques to reduce power consumption.
Earlier generations provide context for the proposed increase. PCIe 5.0 operates at 32 GT/s, while PCIe 6.0 doubled that rate to 64 GT/s. PCIe 6.0 introduced four-level pulse amplitude modulation, known as PAM4, alongside forward error correction and FLIT-based encoding to support higher transfer rates and manage transmission errors.
Connector technology remains under review
PCI-SIG’s public PCIe 8.0 objectives include evaluating new connector technology, but they do not identify a final connector design or specify a replacement for existing PCIe slots. Evaluation does not establish that a particular physical change will be adopted.
Increasing transfer rates places greater demands on the electrical channel, including connectors and circuit-board traces. Signal loss, crosstalk and reflections constrain link design, making physical implementation an important part of developing faster PCIe connections.
Backward compatibility remains a stated objective. The public feature lists do not explain how any eventual connector changes would satisfy that requirement, leaving the relationship between connector development and compatibility unresolved.
Specification timing and intended applications
The draft gives member companies a specification to review and an opportunity to contribute feedback before completion. It does not establish that commercial PCIe 8.0 hardware is ready.
PCI-SIG identifies AI, data centers, high-speed networking, edge computing, quantum computing and high-performance computing among the intended markets. The organization says its aim is to provide the bandwidth and low latency required by data-intensive systems.
The 2028 target concerns release of the completed specification. PCI-SIG’s supplied public announcements do not set a commercial availability schedule for consumer motherboards, graphics cards or SSDs.
