Skip to content
FOR THE LOVE OF ALL THINGS TECH
Semiconductors

TSMC reportedly weighs CoWoS price increase of up to 20%

Hero visual representing TSMC reportedly weighs CoWoS price increase of up to 20%, focused on TSMC CoWoS price increase
Featured visual for TSMC reportedly weighs CoWoS price increase of up to 20%

TSMC is reportedly weighing a price increase of up to 20% for its Chip on Wafer on Substrate (CoWoS) advanced packaging, amid reports of tight capacity for AI processors. The proposal, attributed to supply chain sources, remained unconfirmed by the company as of October 27, 2026.

TSMC has separately acknowledged pressure on back-end production, which includes packaging and testing. At its October 15 earnings call, chairman and CEO C.C. Wei described a shortage and said working with GlobalFoundries was part of the company’s strategy to support customers’ supply needs.

AI chip designs increase packaging and testing demands

CoWoS brings logic chips and high-bandwidth memory, or HBM, together within a single package. TSMC describes the technology as enabling processor cores and memory stacks to sit side by side on an interposer, with dense connections supporting the bandwidth needed for high-performance computing.

Blackwell illustrates the integration involved. In its teardown of Nvidia’s Blackwell B200 platform, research firm TechInsights identified two GPU compute dies and eight HBM3E memory stacks. It also identified TSMC’s CoWoS-L packaging, which uses local silicon bridges to connect components within the package. Each HBM3E stack contains multiple memory dies, with a separate controller die beneath them, the firm said.

Testing is another source of reported capacity pressure. Nomura Securities estimates that final testing for Blackwell takes about four times as long as for the previous-generation Hopper H100, while Rubin could require seven times as long. These figures are analyst estimates rather than confirmed Nvidia test results.

Longer test cycles keep equipment occupied for more time per chip, reducing the number that can be processed with the same installed equipment. Increasing package assembly capacity alone therefore does not address every production constraint; completed accelerators also have to pass through testing.

Reported demand for advanced packaging also extends beyond AI GPUs to server CPUs and custom application-specific integrated circuits, or ASICs. Those products add to the demand manufacturers must accommodate as they plan capacity expansions.

Equipment lead times stretch as requirements rise

Equipment delivery times have reportedly lengthened from three to six months to six to eight months. TSMC is also said to have placed its 2026 equipment orders at existing prices, without seeking the discounts or additional features it would ordinarily negotiate. The reported procurement change remains unconfirmed.

TSMC chief financial officer Wendell Huang addressed rising production costs at the October 15 earnings call. Huang said tool-price inflation was real, alongside higher material and labor costs, although long-term demand remained the main driver of capital expenditure. He said spending in 2026–2028 was expected to be significantly higher than in the preceding three years.

The company’s equipment forecasts had already risen sharply earlier in 2026. Speaking at SEMICON Taiwan on September 2, deputy co-chief operating officer Cliff Hou described repeated increases in TSMC’s anticipated equipment purchases.

Hou used TSMC’s end-2025 forecast as the baseline. The estimate rose to 1.5 times that level after the first quarter before reaching 1.9 times by July, nearly doubling within six months. Those figures concern expected equipment requirements, rather than an equivalent increase in installed production capacity.

“Compared with the pattern 30 years ago, we have never seen the demand increase that much, that frequency of changes,” Hou said.

Capacity forecasts and a U.S. interposer agreement

Goldman Sachs projects CoWoS capacity equivalent to roughly 106,000 wafers per month in 2026 and 227,500 in 2027. These are analyst forecasts for packaging capacity, rather than confirmed TSMC targets or figures for the company’s overall wafer-fabrication capacity.

GlobalFoundries announced a manufacturing agreement with TSMC on October 8, 2026, to establish a U.S. supply of silicon interposers for the CoWoS ecosystem. GlobalFoundries valued the agreement at $2 billion and said it has an initial term of five years. The agreement also provides a framework for future capacity expansion, GlobalFoundries said.

The company plans to add manufacturing capacity at its Malta, New York, facility. GlobalFoundries expects volume production to begin ramping during the first half of 2028. That schedule places the planned additional interposer supply beyond the period covered by the 2026 and 2027 packaging-capacity forecasts.

Interposers provide connections within advanced chip packages, but their manufacture is one part of the broader packaging process. The agreement adds a planned source of that component, while the reported constraints also involve package assembly, testing throughput and equipment availability.