TSMC is reportedly considering higher chip-production prices for 2027, including baseline increases of between 5% and 10% for advanced manufacturing processes. Some customers seeking capacity beyond their previously agreed volumes could face a larger adjustment, although neither the pricing structure nor its implementation schedule has been publicly confirmed.
The most eye-catching figure is a potential increase of roughly 25% for certain orders. That would not be a universal price rise. It represents a possible combination of a higher baseline rate and an additional premium for customers requesting more high-performance computing capacity than originally planned.
The distinction matters because foundry contracts are not simple retail price lists. Rates can vary by process node, production volume, chip design, capacity commitment and the customer’s broader relationship with the manufacturer. A headline percentage therefore cannot be applied evenly across every chip made by TSMC.
Advanced nodes could see the broadest increase
The unconfirmed pricing framework would raise baseline rates for advanced process technologies by approximately 5% to 10%, with the precise adjustment depending on the node and customer. TSMC generally groups its 7-nanometer-class and smaller manufacturing technologies into its advanced-node category.
Those processes are used for sophisticated processors serving applications such as smartphones, high-performance computing and AI infrastructure. Demand from these markets makes access to leading-edge production capacity strategically important, but the reasons behind any prospective price adjustment have not been formally detailed.
Customers asking for additional high-performance computing capacity could reportedly encounter another 10% to 15% premium on top of the baseline change. Under the highest proposed combination, the total increase for that extra capacity could approach 25%. This scenario remains unconfirmed, and there is no public indication that every additional order would attract the maximum premium.
The structure would effectively distinguish between capacity already covered by customer agreements and extra production requested later. If implemented, that could encourage chip designers to make earlier volume commitments rather than depend on securing additional capacity as their needs change.
That calculation is especially relevant for high-performance products, where demand can shift quickly and production planning begins well before a finished processor reaches the market. Still, the available information does not establish how TSMC might define excess demand, which customers would be affected or whether premiums would vary between manufacturing processes.
Mature manufacturing processes may also cost more
Potential changes are not limited to TSMC’s newest technologies. Pricing for mature processes, including the company’s 12nm, 16nm and 28nm-class nodes, is reportedly under review as well. Some adjustments could approach 10%, while others may be smaller. Final node-by-node rates have not been made public.
Mature nodes remain useful for products and components that do not require the density or performance of leading-edge manufacturing. They also serve designs for which cost, established production methods and long-term availability can matter more than moving to the smallest available process.
A broad adjustment spanning both advanced and mature production would give customers fewer opportunities to avoid higher fabrication costs simply by using an older process. Even so, the effect would differ substantially by product. A processor manufactured on a leading-edge node has different cost and capacity requirements from a supporting component built with a mature technology.
The percentages also describe foundry services rather than complete devices. Fabrication is only one part of a finished product’s cost, alongside chip design, packaging, memory, storage, displays, logistics and other components. It would therefore be premature to translate a possible foundry increase directly into an equivalent increase for laptops, graphics cards, smartphones or servers.
Why extra capacity carries the biggest uncertainty
The proposed premium for additional capacity is the least settled part of the picture. A baseline adjustment can be incorporated into planned production budgets, while a separate charge for extra volume would depend on demand that exceeds an existing commitment. That makes the upper-end 25% figure a conditional scenario rather than the expected increase for a typical wafer order.
For chip designers, the practical impact would depend on how much production they have already reserved and how accurately those commitments match future demand. A customer with sufficient contracted capacity might face only the baseline adjustment. One that needs substantially more output could be exposed to the additional premium if the proposed structure is adopted.
This arrangement could also complicate pricing decisions further down the supply chain. Customers would need to determine whether to absorb higher manufacturing costs, seek savings elsewhere or adjust the prices of products using the affected chips. Those decisions would be company- and product-specific, so a general increase in TSMC’s rates would not guarantee that every consumer device becomes more expensive.
Capacity availability is another unknown. A premium may matter less than whether the required production slots are available at all, particularly for chips that cannot be moved easily to a different process or foundry. Porting a complex design is not equivalent to switching suppliers for a standard component; it can require engineering work, validation and changes to the production schedule.
Final pricing and timing remain unconfirmed
TSMC has not publicly confirmed a comprehensive 2027 price schedule matching the percentages under discussion. The reported start of 2027 would give customers time to account for revised manufacturing costs, but a firm implementation date has not been established publicly.
That leaves the figures best understood as possible parameters rather than settled rates. Baseline increases of 5% to 10% appear to form the core of the prospective plan, while the largest adjustment would apply only in the reported scenario involving extra high-performance computing capacity.
Until formal terms emerge, the implications for chip designers and device buyers remain uncertain. The eventual effect will depend on which nodes receive increases, how customer contracts are structured, whether additional-capacity premiums are adopted and how much of any added cost moves through the supply chain. For now, the prospect of higher TSMC pricing is significant, but the 25% figure should not be treated as an across-the-board increase.