IBM is making a big semiconductor claim: a chip architecture it calls nanostack could point toward what the company describes as the world’s first sub-1 nanometer chip technology for AI data centers.
The headline number is easy to misread. IBM says the architecture could support nearly 100 billion transistors on a chip roughly the size of a human fingernail, nearly twice the transistor density of its prior generation. That claim has not been independently verified, and it should be treated as a research projection rather than a commercial product spec.
The more important point is not that IBM has built transistors with physical features smaller than one nanometer. It has not claimed that in the literal sense. Instead, IBM is using the language of chip process nodes, where names like 3nm, 2nm, and now 0.7nm no longer map cleanly to the actual dimensions inside a chip.
That distinction matters for anyone trying to understand what this means for AI hardware, future CPUs and GPUs, or the long-term cost of compute. IBM’s pitch is about a new way to stack transistors vertically, not a simple continuation of making every feature smaller on a flat surface.
What IBM Means By Sub-1 Nanometer
IBM describes the technology as a 0.7-nanometer node, also called a 7 angstrom node. One nanometer equals 10 angstroms, so the name fits the process-node branding. But node names have become marketing shorthand for a broader generation of chip technology, not a ruler placed across a transistor gate.
That has been true for years. In older chip generations, the node name was more closely tied to real physical feature sizes. In modern leading-edge chips, the node label is better understood as a package of density, performance, power, and manufacturing improvements. So IBM’s sub-1 nanometer claim is best read as a statement about expected class of performance and scaling, not as proof that every relevant feature has crossed below one nanometer.
The company’s proposed answer to the scaling problem is nanostack. The architecture vertically stacks transistors in a staggered arrangement, letting designers pack more transistor capacity into the same footprint. It builds on IBM’s earlier nanosheet work, which the company previously positioned as a foundation for its 2-nanometer chip generation. That lineage has not been independently verified here in every technical detail, but the broad direction is clear: the industry is trying to move beyond conventional planar shrinking by using more three-dimensional transistor structures.
How Nanostack Changes The Layout
At the basic level, IBM describes nanostack as two transistors stacked and bonded together. Each transistor is described as using three nanosheets, each 5 nanometers thick, with about 9 nanometers between sheets. Those figures come from IBM’s technical framing and have not been independently verified.
The buyer-relevant takeaway is simpler: chip scaling is increasingly about architecture and packaging, not just smaller dimensions. If a chip designer can place more functional transistor structures in the same area without a proportional increase in power draw, that can help data centers chase more compute without simply adding more racks, more cooling, and more electricity demand.
That is why IBM is tying the work directly to AI data centers. AI workloads are hungry for dense compute, high-bandwidth memory access, and lower energy per operation. Any credible path to more transistor density and better efficiency will get attention from hyperscalers, accelerator designers, and foundries planning chips years before they ship.
The Performance Claims Are Promising, But Still Projections
IBM projects that nanostack could enable up to 50 percent higher compute performance or 70 percent better energy efficiency compared with its previous 2-nanometer node technology. The company also claims a 40 percent scaling improvement for SRAM, a type of fast on-chip memory that is important for many AI workloads.
Those figures are not the same as product benchmarks. They should be treated as company projections tied to research work, not as performance numbers for a chip that buyers can order.
| Claimed Area | IBM’s Stated Direction | How To Read It |
|---|---|---|
| Transistor density | Nearly 100 billion transistors on a fingernail-size chip | A research claim that has not been independently verified |
| Compute performance | Up to 50 percent higher than IBM’s prior 2nm generation | A projection, not a commercial benchmark |
| Energy efficiency | Up to 70 percent better than IBM’s prior 2nm generation | Potentially important for AI data centers if it reaches production |
| SRAM scaling | 40 percent improvement | Useful if validated, because on-chip memory scaling has become harder |
The SRAM part may be especially important. SRAM supports fast read and write operations on chips, but it also takes up valuable die area and can be power-hungry. IBM says its staggered-channel design for SRAM bit cells reduces cell height and allows more SRAM in the same space. That figure has not been independently verified, but it speaks to a real pressure point in AI chip design: memory is often just as important as raw compute.
What This Means For Chip Buyers
There is no near-term buying decision here. IBM does semiconductor research, but it does not directly manufacture the kind of commercial chips that would land in AI servers, laptops, or phones. Its influence comes through research, licensing, and partnerships with chip manufacturers.
IBM has worked with Rapidus in Japan around 2-nanometer manufacturing and with Samsung on related semiconductor technology. For nanostack, IBM has not named specific commercialization partners. The company’s public timeline is broad: production could begin as early as the next five years, with a more likely window sometime within a decade.
That makes this announcement relevant for roadmaps, not procurement. Data center operators, enterprise AI buyers, and hardware teams should not expect this technology to change accelerator pricing or availability in the next buying cycle. The practical questions are longer term:
- Can the architecture be manufactured at commercial yield?
- Can foundry partners adapt it without pushing costs too high?
- Will the projected performance and efficiency gains survive real product constraints?
- Can SRAM scaling improve enough to help AI workloads that are limited by memory movement?
For buyers, the most realistic reading is that nanostack is another sign that chipmakers are fighting hard to extend the economics of advanced silicon. It is not a product announcement. It is not a guarantee that AI compute will get cheaper. But if the approach works, it could help future CPUs, GPUs, and AI accelerators deliver more performance per watt.
The Bottom Line
IBM’s sub-1 nanometer claim is attention-grabbing, but the useful story is more technical and more grounded. This is about stacking transistors to keep chip density moving as traditional scaling gets harder.
The company’s claims around density, performance, energy efficiency, and SRAM scaling are ambitious and not independently verified. Still, the architecture points in the direction the semiconductor industry has been moving for years: more vertical structures, more complex transistor designs, and more pressure to squeeze efficiency out of every square millimeter of silicon.
For now, nanostack belongs in the category of serious research with major commercial implications if it reaches production. The first buyers affected by it will not be consumers shopping for a device. They will be chip companies, foundries, and AI infrastructure players deciding what the next decade of compute should be built on.