A multi-university team says it has built the first monolithic 3D memory-and-logic chip produced at a U.S. commercial foundry, a milestone that could make stacked compute architectures far more practical than today’s packaging-heavy approaches.
Engineers from Stanford, Carnegie Mellon, the University of Pennsylvania, and MIT developed the prototype and fabricated it with SkyWater Technology, aiming to prove that monolithic 3D integration can move out of university cleanrooms and into real foundry flows.
Monolithic 3D, not chiplets
Unlike chiplet-style designs that package multiple finished dies together, monolithic 3D integration builds layers sequentially on the same wafer. The payoff is a dense web of vertical connections that can dramatically shorten the distance between memory and compute—one of the core bottlenecks in modern AI and HPC systems.
The key challenge is heat: you can’t bake a new layer at traditional high temperatures without damaging what’s already underneath. The team says it solved that by keeping the process within a low thermal budget designed to protect previously fabricated circuitry.
What’s inside the stack
The prototype was manufactured on SkyWater’s 200mm production line using a mature 90nm/130nm class process. The stack combines:
- Conventional silicon CMOS logic
- Resistive RAM (RRAM) layers
- Carbon nanotube field-effect transistors (CNFETs) integrated in the back end of line (BEOL)
All of it was fabricated under a thermal ceiling of about ≤415°C, which is the enabling trick for stacking without breaking the earlier layers.
Early results: 4× throughput at the same footprint
In early hardware testing, the researchers report roughly 4× read bandwidth and 4× compute throughput versus a comparable 2D baseline (with similar latency and footprint). In other words: the gains come from shorter, denser data paths—not simply scaling area.
Simulated stacks go further
The team also modeled taller multi-tier versions in simulation. Those designs delivered up to 12× performance improvements on AI-style workloads, including models derived from Meta’s LLaMA architecture.
Longer-term, the researchers argue monolithic 3D scaling could open a path to 100×–1,000× improvements in energy-delay product—a projection, not a measured claim—by stacking vertically rather than relying solely on shrinking transistors.
Why a foundry demonstration matters
Academic labs have shown monolithic 3D concepts before, but the team’s main pitch is manufacturability: this was built in a commercial foundry environment on a standard production line, not a bespoke research process.
“Turning a cutting-edge academic concept into something a commercial fab can build is an enormous challenge,” said co-author Mark Nelson, vice president of technology development operations at SkyWater Technology.
The work was presented at IEEE IEDM 2025, held Dec. 6–10.