HPE is showing where its next generation of Cray supercomputing hardware is headed, and the direction is clear: far more compute packed into the same rack footprint.
The company has presented the HPE Cray GX5000 as a rack-scale platform built around AMD’s upcoming EPYC Venice processors. The most eye-catching configuration is described as targeting up to 81,920 CPU cores in a single 42U rack, though the exact processor configuration and final Venice specifications have not been publicly confirmed.
That caveat matters. AMD has not released the full specs or performance figures for Venice, so the numbers around the GX5000 should be treated as a preview of HPE’s design target rather than a complete product sheet. Still, the system gives a useful look at how HPE is thinking about the next phase of high-performance computing infrastructure: bigger CPU counts, more memory close to the processors, liquid cooling throughout the rack, and networking designed for tightly coupled workloads.
A rack-scale design built around AMD Venice
At the center of the Cray GX5000 design is the HPE Cray GX250a compute blade, which HPE has shown as a dense building block for AMD EPYC Venice processors. Publicly discussed configurations point to eight Venice CPUs per blade, but because Venice remains unreleased, the final processor details are still not settled.
The broader system appears designed to combine compute, memory, storage, power delivery, liquid cooling, and networking into a tightly integrated rack rather than treating each server node as a more isolated box. That is the real story here. HPE is not only leaning on a future CPU with more cores; it is arranging the surrounding hardware so those cores can be fed, cooled, and connected at scale.
A fully populated rack has been described as using 80 multi-node motherboards and supporting up to 1.28PB of memory. Those figures have not been independently verified, but they suggest the class of system HPE is preparing for: machines intended for large simulations, AI model work, engineering analysis, and other workloads where raw density and memory bandwidth can matter as much as per-chip performance.
The Venice platform is also expected to emphasize memory bandwidth. Each processor has been described as connecting to 16 memory channels, although that detail remains tied to unreleased silicon. The memory modules shown with the system appear to be liquid-cooled and close to standard DIMM form factors, reinforcing how much of the design depends on controlling heat as component density rises.
Cooling and networking are part of the pitch
The GX5000 is not just a CPU story. HPE’s Cray systems are built for large clusters, so networking and cooling are core parts of the platform rather than supporting details.
The rack has been shown with Slingshot 400 networking hardware, with HPE indicating a path toward future Slingshot 800 compatibility. Networking modules are arranged in side pods and connected to the compute hardware through dedicated interfaces, a layout meant to support high-bandwidth communication while keeping cable routing more manageable at rack scale.
HPE also displayed a coolant distribution unit described as capable of handling 1.6MW of cooling capacity for large installations. That number has not been independently verified, but it fits the broader direction of modern HPC infrastructure. As systems put more processors, memory, and networking into each rack, air cooling becomes less practical for the most demanding deployments.
The hardware shown with the system included local Samsung E1.S EDSSF SSDs positioned above several processor cold plates. HPE representatives described those drives as high-speed scratch storage for temporary data processing, a common need in systems that have to move large working data sets quickly without turning every operation into a trip across the wider storage fabric.
Why the Venice question matters
The unresolved piece is AMD Venice itself. AMD’s EPYC 9965 already pushed server CPU density with 192 cores, and Venice is expected to move the line again. But without official public specifications, it is too early to treat any implied per-socket core count or performance estimate as final.
That uncertainty is why the GX5000 should be read less as a finished benchmark story and more as a signal of where HPE and AMD are aiming. If the rack targets hold, the system would represent a major density jump for x86-based supercomputing infrastructure. If the final Venice specs or product timelines shift, the exact shape of that jump could change.
For buyers and operators of large HPC environments, the practical takeaway is not a simple core-count headline. It is that next-generation Cray infrastructure is being engineered around rack-level density from the start. Cooling, memory, local scratch storage, and network layout are all being treated as part of the same problem: how to keep increasingly powerful CPUs useful once they are packed into production-scale systems.
A firm public launch timeline has not been confirmed, and the missing Venice details leave important questions open. But the Cray GX5000 already shows the next battleground for supercomputing hardware: not just faster processors, but denser systems that can keep those processors busy without overwhelming the rack around them.