Imec has presented what it describes as the world’s first quantum dot qubit device fabricated with High-NA EUV lithography, a notable step toward bringing one branch of quantum hardware closer to advanced semiconductor manufacturing.
The Belgian semiconductor research institute showed the device at ITF World on May 19, 2026. According to imec, the prototype uses silicon quantum dot spin qubits, with control-gate features patterned at gaps of about 6 nanometers between plunger and barrier gates. That detail matters because quantum dot devices depend heavily on extremely tight, repeatable gate spacing.
The announcement should not be read as proof that large-scale, fault-tolerant quantum computers are now around the corner. It is better understood as a manufacturing milestone. Imec is trying to show that one promising quantum architecture can be made with the same class of industrial tools being prepared for future leading-edge processors, AI accelerators, and memory.
That distinction is important. Quantum computing has many unresolved physics, control, error-correction, and systems-engineering challenges. But for silicon spin qubits, the manufacturing question is central: can researchers move from carefully made lab devices to repeatable wafer-scale production?
Imec’s answer, at least in this early demonstration, is that High-NA EUV may be precise enough to help.
Why the Manufacturing Method Matters
Quantum computing’s biggest practical obstacle is scale. Researchers have already demonstrated working qubits using several architectures, including superconducting circuits, trapped ions, photons, and silicon-based devices. The harder problem is building machines with enough reliable, controllable qubits to run useful fault-tolerant workloads.
That is why imec’s announcement is not mainly about raw qubit performance. The key claim is that the device was fabricated using a production-oriented semiconductor process on advanced lithography equipment, rather than a purely custom lab flow.
Silicon quantum dot spin qubits are often treated as one of the more manufacturing-friendly quantum approaches because they are based on silicon nanostructures and can, in principle, fit into parts of the CMOS manufacturing ecosystem. That does not mean they can simply be dropped into today’s CPU or GPU production lines. It means the architecture has a closer relationship to conventional chipmaking than some quantum approaches that require more specialized fabrication environments.
In a silicon quantum dot spin qubit, an electron is confined inside a tiny silicon structure. Information is encoded in the electron’s spin state, while nearby gates help control the behavior of that electron and its interaction with neighboring quantum dots. The concept is compact; the implementation is not.
The spacing and precision of the control gates are critical. If neighboring quantum dots are too far apart, coupling can be weak. If the structures vary too much across a wafer, device behavior becomes difficult to reproduce. Moving toward useful quantum processors means making these tiny structures consistently, not just once under ideal lab conditions.
Imec says its High-NA EUV process produced qubit arrays with approximately 6nm gaps between key gates. That figure should be treated as imec’s reported result, but it is the central technical detail behind the announcement.
What High-NA EUV Adds
High-NA EUV, or high numerical aperture extreme ultraviolet lithography, is the next major step in advanced chip patterning. Current EUV systems use a numerical aperture of 0.33, while High-NA EUV raises that to 0.55. In practical terms, the higher numerical aperture allows smaller features to be printed with improved patterning capability.
The technology was developed primarily for future leading-edge logic and memory manufacturing, not quantum devices. That is what makes imec’s demonstration interesting. The same equipment family being positioned for next-generation semiconductor scaling is now being tested against quantum hardware requirements.
High-NA EUV tools are still at the early edge of semiconductor deployment. Intel received ASML’s first High-NA EUV development system in 2023, and later announced installation of a newer commercial-production-oriented High-NA tool for work on future process technology. Imec has also brought High-NA EUV into its 300mm research cleanroom.
Those details matter because High-NA EUV is not a mature, widely distributed production tool yet. It is expensive, complex, and still being integrated into the semiconductor roadmap. If quantum hardware can make use of it this early, it suggests silicon-based quantum devices may be able to follow part of the same manufacturing learning curve as advanced chips.
That does not guarantee faster commercialization. It does, however, make the path more concrete. Instead of building an entirely separate fabrication base for every quantum architecture, silicon quantum dot developers may be able to draw on tools, process controls, metrology, and wafer-scale methods already being refined by the chip industry.
The Real Breakthrough Is Not the Qubit Type
Silicon quantum dot spin qubits are not new. Researchers have worked on them for years, and previous devices have been made with other lithography and fabrication methods. Imec’s result is notable because it connects that architecture to High-NA EUV patterning.
That is a narrower claim than saying imec has solved quantum computing. It is also a more useful one.
The field does not need one more vague promise that quantum machines will soon outperform classical computers across broad categories of work. It needs evidence that the hardware can become more repeatable, more compact, and more manufacturable. For silicon spin qubits, that means shrinking and controlling the electrode patterns that define and manipulate the quantum dots.
Imec’s demonstration points at three possible advantages:
- Smaller gate spacing, which can improve coupling between quantum dots when the rest of the device physics supports it.
- Compatibility with 300mm semiconductor research infrastructure, which is important for future wafer-scale process development.
- A closer connection between quantum hardware development and the semiconductor industry’s existing lithography roadmap.
Those are manufacturing advantages, not proof of a complete quantum system. A useful machine still needs high-fidelity qubit operation, low error rates, scalable control electronics, cryogenic integration, error correction, and software stacks that can turn the hardware into practical computing capacity.
Why Silicon Spin Qubits Keep Drawing Attention
Silicon spin qubits are attractive because they are physically small and are based on materials already familiar to the chip industry. If they can be manufactured with sufficient precision and controlled at scale, they could allow dense quantum processors that benefit from decades of semiconductor process knowledge.
That remains a conditional statement. Silicon compatibility helps, but it does not erase the difficult parts of quantum engineering. Quantum devices are extremely sensitive to noise, defects, variability, and control errors. A process that works for classical transistors still has to be adapted and validated for quantum behavior.
The appeal is that the semiconductor industry already knows how to do something quantum computing badly needs: make enormous numbers of tiny structures with tight tolerances and gradually improve yield over time. Imec’s work asks whether that industrial discipline can be applied to silicon quantum dots before the field gets stuck in small-batch experimental fabrication.
If that approach succeeds, the likely first users would not be consumers or typical PC buyers. Early useful quantum systems would more likely serve national labs, hyperscalers, pharmaceutical researchers, materials companies, defense organizations, and other groups with problems that justify specialized computing infrastructure.
Potential applications include molecular simulation, materials research, some optimization problems, cryptography-related analysis, and modeling of complex quantum systems. Many of those use cases are still research targets rather than everyday commercial products.
What Happens Next
The next questions are practical. Imec and its partners will need to show that the process can be repeated, that device variability can be controlled, and that the resulting qubits perform well enough under real operating conditions. Patterning a device is not the same as proving a scalable quantum processor.
Still, this is a meaningful signal. High-NA EUV was built for the future of classical semiconductor manufacturing. Imec has now shown that it can also be applied to one of the quantum architectures most closely aligned with silicon chip production.
That makes the announcement important for a specific reason: it narrows the gap between experimental quantum devices and industrial manufacturing practice. The breakthrough is not that quantum computers are suddenly imminent. It is that one possible route to building them at scale now looks more connected to the tools already shaping the next generation of chips.